Photolithography (which may also be referred to as just ‘lithography’) is a well-known technique used in semiconductor device fabrication to provide three-dimensional patterns (or shapes or features) to a semiconductor structure. The terms “patterns”, “shapes” and “features” are interchangeably used in the present application. The three-dimensional patterns may be located within a semiconductor substrate itself or they can be formed on a surface of a semiconductor substrate. Photolithography generally includes the steps of applying a photoresist material to a surface of a structure having at least one material layer that needs patterning, exposing the applied photoresist material to a pattern of radiation and developing the pattern into the photoresist material utilizing a resist developer. The pattern in the photoresist is then transferred to the underlying material layer(s) of the semiconductor structure utilizing an etching process such as reactive-ion etching, ion beam etching, plasma etching or laser ablation. Depending on the material layer(s) being etched, the remaining photoresist can be removed prior to or after the etching process.
The patterns provided by photolithography are three-dimensional in that they have a width, height and length associated therewith. Examples of three-dimensional patterns that can be formed utilizing photolithography include, but are not limited to: trenches for isolation regions, vias and lines for device metallization, and gate stacks for field effect transistor fabrication.
One major drawback with conventional photolithographic processes in patterning crystalline materials is that the patterning of features that are comparable in scale to the wavelength of exposure radiation in such crystalline materials is limited by diffraction and interference effects. Optical proximity constraint (OPC) techniques can help to mitigate these effects, but fundamental limitations remain in how sharply these features can be defined. In particular, the corners of such features tend to be rounded with a radius on the order of the light wavelength. This rounding can limit circuit density since key material layers must be overlaid in a way that avoids these corners.
FIG. 1 shows a fragment of a typical pattern that is formed into a crystalline Si-containing material. As shown, prior art photolithographic processes provide a patterned region 100 that has rounded internal and external corners 102A and 102B, respectively. When polygates 104A and 104B are formed over the patterned region 100, the channel widths of these devices vary. In particular, polygate 104A has a wider channel width 106A at the internal corner 102A than the channel width of polygate 104B at the external corner 102B.
In view of the above, a method is needed which overcomes the problems with prior art photolithographic processes, particularly corner rounding. In particular, a method is provided in which the ideal structure shown in FIG. 2 is provided. The ideal structure shown in FIG. 2, which is achieved utilizing the method of the present invention, includes a crystalline Si-containing material that has shapes which have uniformly straight sides or edges and well-defined corners, i.e., corners that are substantially square, i.e., orthogonal. By ‘substantially square’, it is meant that the shapes provided in the crystalline Si-containing material by the present invention have wall portions that are at 90° to each other, as seen in a top view, for example, the view illustrated in FIG. 2.